Exploring the use of the finite element method for electromigration analysis in future physical design

Addressing electromigration (EM) during physical design has become crucial to ensure reliable integrated circuits. Simulation methods, such as the finite element method (FEM), are increasingly overwhelmed by the complexity of the task. With further technology scaling, it is predicted that FEM will not be usable anymore for a full-chip EM analysis due to complexity reasons. To address this bottleneck, we present a new methodology of FEM-based full-chip EM analysis for future technologies down to 10 nanometer feature sizes. Our solution reduces analysis costs significantly by establishing pre-validated layout patterns without loosing accuracy of the verification results. Our full-chip meta-model EM analysis allows speedups of at least 10X compared to current FEM-based verification methods.