Reliability and performance tradeoffs in the design of on-chip power delivery and interconnects

The performance of CMOS integrated circuits has always been, and continues to be, limited by reliability considerations. Performance, reliability, and cost are traded off through voltage and temperature specifications. Higher operating voltage raises performance but impacts reliability both directly and through increased temperatures unless extra cooling is supplied. Lower temperatures yield higher performance and higher reliability but also higher cost. As silicon technology scales, these trade-offs are becoming more pronounced. While hot carrier injection may be becoming less significant as semiconductor technology scales to thinner gate oxides, other mechanisms are becoming more significant. The temperature acceleration of oxide breakdown is increasing with decreasing thickness (Degraeve et al., 1999), current densities are increasing, further stressing electromigration, and inductive noise effects are becoming more significant, while soft error susceptibility is increasing (Dai et al., 1999). There are many mechanisms that can lead to the failure of an integrated circuit. Hot carrier injection has been a significant issue, but has been surpassed by other mechanisms as CMOS technology has advanced into the deep submicron regime. In this paper, we focus mainly on the design and validations issues associated with oxide wear-out failure mechanisms.