Design and analysis of FIR filters using low power multiplier and full adder cells

In this paper, presents the application of minimize the Power, Area in CMOS VLSI circuits. The proposed FIR Filter is designed by using full adder and multiplier. The design of full adders for low power is obtained and low power units are implemented on the proposed multiplier and the results are analyzed for better performance. The FIR filters are designed in both direct form method and Transposed form method. The low power filters are simulated for linear phase. A new technique called folded filters is also designed in linear phase. The designs are done by using TANNER S-EDIT tool and simulated using T-SPICE.