Determination of key parameters for SEU occurrence using 3-D full cell SRAM simulations

A 3-D entire SRAM cell, based on a 0.35-/spl mu/m current CMOS technology, is simulated in this work with a DEVICE simulator. The transient current, resulting from a heavy ion strike in the most sensitive region of the cell, is studied as a function of the LET value, the cell layout and the ion penetration depth. A definition of the critical charge is proposed and two new methods are presented to compute this basic amount of charge only using SPICE simulations. Numerical applications are performed with two different generations of submicron CMOS technologies, including the determination of the sensitive thicknesses.