A study on the ternary DCG circuit design with matrix equation

Multiple-valued logic theory and the locally computable combinational circuit realization technique in making VLSI chips have become a very important subject of study. These fields are being actively researched in order to overcome the limitations and the problems in the existing method of binary digital logic circuit realizations. These fields also have the prospect of increasing the processing speed as well as the amount of information that can be stored in the same circuit area. In this paper the algorithm for designing highly parallel multiple-valued logic circuit on the basis of the heretofore mentioned methods with improvements using the matrix equation about cyclic characteristic nodes is discussed. Some examples are shown to demonstrate the usefulness of the proposed method in this paper.