Methodology for design of optimum NOC based on IPG

High performance embedded applications are developed using system-on-chips (SoCs) which in turn include silicon intensive, integrated application processors. These SoCs integrate multi-core processor (i.e., ARM Cortex9 or A15) with variety of memory interface controllers, communication interface controllers and special purpose accelerators. Traditionally bus matrix is used for integrating these intellectual properties - cores (IPs). Bus based architectures are not scalable and consume more area and power, which has fueled design of network on chip (NOC). A customized NOC is further more efficient. In this paper, a methodology for customized NOC architecture is introduced considering various aspects of NOC as well as the SoC. Policies for optimizing Bandwidth requirement, size of the IP (area or gate count), lP location for optimum path lengths are discussed. Policies in turn form methodology for optimum NOC. As IPs in SOC increase in numbers, NOC for interconnecting every IP may result in over networking. Sometimes, performance of router is under utilized. On the other hand, for closely coupled IPs direct port to port connections are suitable than NOC as they communicate heavily. IPs which talk one at a time are grouped together and common local bus architecture is suitable for them. Outside group they talk through NOC. Or routers with less number of ports gives better results. Proper grouping and layout will reduce complexity. Here I am proposing a methodology for handcrafting NOC among intellectual property core groups (IPGs), inside and outside of the groups. Final outcome is, reduced number of routers required and optimized physical design of SoC.