A generalized block distribution algorithm for fast carry-skip adder design

In this paper, we describe a generalized block distribution algorithm to determine the block sizes. Furthermore, we employ an alternative carry-skip circuit in each block to accelerate the carry propagation speed and lower the power consumption. Various supply voltages were used during the simulation phase. The simulation results reveal that the proposed scheme can provide faster speed and lower power consumption than those of the existing carry-skip adder. These power and speed advantages are maintained down to a 1.2 V power supply. It is suitable for low-power high-speed adder implementation.