High speed and high-area efficiency non-volatile look-up table design based on magnetic tunnel junction

Continual growth in the size and functionality of FPGAs over past few years has resulted in an increasing interest in their use for high speed applications. However, the execution speed is limited by the memory access speed and the whole function is affected due to the great amount of data. This paper introduces a novel high speed and high-area efficiency MRAM-based non-volatile look-up table (nvLUT) to overcome the effect of high resistance introduced by the increasing number of inputs. This nvLUT reduces the sense delay and MTJ count by 55 % and 47%.