Majority Voting-Based Reduced Precision Redundancy Adders

Fault-tolerant systems are usually implemented with triple modular redundancy (TMR)-based protection techniques which has a huge area and power overhead. Previous works have shown that this overhead can be improved by using reduced precision redundancy (RPR)-based approaches for intrinsically precision-tolerant applications like image and video processing. The error detection and steering logic required in the RPR schemes utilize subtraction and comparisons which are more complex hardware operations than TMR voting. This overhead is affordable for complex hardware structures, for example, finite impulse response filters, but for simple structures like adders, it can be significant. In this letter, it is shown that combining the traditional TMR voting with the RPR brings up considerable savings in area and power budget when applied to very-large-scale integration adder circuits.