Understanding the thermal challenges of high-performance mobile devices with a detailed platform temperature model

Modern high-performance electronics are embedded in smartphones, self-driving automobiles, and augmented reality wearable. These computing platforms are high performance and multifunctional. One of the major performance limiting factors in these platforms is the poorly designed thermal solution that is triggered to prevent overheating at the processor transistor junction and at the platform surface. Even though the dynamic voltage and frequency scaling (DVFS) feature widely available in modern processors can be used as a control knob in processor temperature management, its associated performance cost is tremendous and the response time for temperature control is significant. In this work, we build a detailed finite element model to predict the temperature behavior of a tightly-packaged, high-performance embedded platform, from the system level down to the processor architecture level. We first characterize the thermal response of real-world, representative mobile workloads and perform parametric studies to predict the processor junction and platform surface temperature based on the properties of the platform. We validate the proposed temperature model used to predict the maximum temperature at the processor chip and the platform surface. Our preliminary results show that the physical construction (such as air gaps) and the floor plan of the multi-layer platform have a profound effect on the system temperature behavior.