Adaptable VLIW processor: The reconfigurable technology approach

Traditional processor design approaches using CISC and RISC philosophies suffer from low performance. One of alternative approaches to improve system performance is instruction level parallelism (ILP). Among the processor architectures supporting ILP, very long instruction word (VLIW) processors offer some advantages such as low power consumption and hardware complexity. In this paper, we introduce our adaptable VLIW processor that can adapt its functionality and organization at design time so that the processor configuration is optimized for a specific application. Based on the reconfigurable technology approach, we propose our design framework that allows users to configure the VLIW processor according to parallelism level of a particular application. The design framework also helps designers implement the processor on FPGA platforms without knowing HDLs. We conduct our experiments by synthesizing the proposed VLIW processor with four different FPGA families and by developing three applications using our proposed VLIW processor. The synthesis results show that our processor can work at up 174.89 MHz when implemented with the Xilinx Virtex 7 FPGA devices. The experimental results show that the proposed VLIW processor can achieve speed-ups by up to 22.6× when compared to the NIOS II RISC-like softcore processor at the same working frequency.