Wide-area clock distribution using controlled delay lines

This paper describes a clock distribution strategy adequate for wide-area synchronisation, applicable to VLSI, WSI and MCM systems. This strategy is described in terms of Controlled Delay Lines. Local clock multiplication is proposed to solve possible phase ambiguities. Implementation issues are also discussed. Simulations using DLLs with extreme parameter variations are presented in the last section. Sub-nanosecond phase accuracy is shown for wafer size areas.