Synthesis and analysis of high-order cascaded continuous-time /spl Sigma//spl Delta/ modulators

In this paper, synthesis and analysis of high-order cascaded continuous-time /spl Sigma//spl Delta/ modulator have been explored. A simple mixed-mode methodology is used to synthesize the cascade continuous-time /spl Sigma//spl Delta/ modulator. Mixed-mode simulation is performed by MATLAB. A 3rd-order 2-1 cascaded case is demonstrated, also the nonlinearities of high order continuous-time cascaded /spl Sigma//spl Delta/ modulator are analyzed, such as clock jitter and loop delay.