A 0.7 /spl mu/m CMOS clock recovery circuit for 622 Mb/s SDH systems

A clock recovery circuit for SDH STM-4 applications is described. The circuit has been implemented in a 0.7 /spl mu/m CMOS technology. A digital VCO has been designed for the 622 MHz frequency. The chip sustained working frequencies from 550 up to 700 MHz. The recovered clock jitter (peak-to-peak) is under 150 ps, for SDH STM-4 data signals.