Efficient drivers, receivers and repeaters for low power CMOS bus architectures

New driver/receiver CMOS circuits design, for low-power VLSI applications, are proposed. They are based on the low swing technique. A significant reduction in power dissipation is achieved, due to the reduced swing voltage on the interconnection loads. Comparisons of the delay time of the proposed circuits with the conventional CMOS driver/receiver are presented. For different values of supply voltage, using 0.5 /spl mu/m process technology, SPICE measurements show up to 27% improvement in the total driver/receiver power-delay product. Finally, circuits as repeaters are proposed for long interconnections.