Design Techniques Targeting Low-Area–Power-Delay Product in Hyperbolic CORDIC Algorithm

The COordinate Rotation DIgital Computer (CORDIC) algorithm is a famous technique for realizing complex arithmetic functions using simple shift-add operations. This paper presents a novel completely scaling-free CORDIC algorithm in rotation mode for high performance hyperbolic computations. We target algorithm level improvements to achieve low area and power-delay product on FPGA. Instead of complex search algorithms, we use the most significant one bit detection technique for micro-rotation sequence identification, which helps in significantly reducing the number of pipelining stages. The proposed technique uses mathematical identities to extend the range of convergence. The eight-staged pipelined architecture implementation requires a ROM in the preprocessing unit for storing the initial coordinate values, while the ROM for storing the elementary angles is eliminated. The FPGA implementation of the proposed processor requires 46.35% less gates and has 31.81% less delay when compared with Xilinx Core IP-CORDIC v3.0. Moreover, on an average it consumes 75.96% less power when compared with Xilinx CORDIC v3.0. Hence, the proposed technique provides an area–power-delay efficient VLSI implementation for calculating hyperbolic functions and exponents. The detailed algorithm design, along with FPGA implementation and area and time complexities, is presented in this paper.