Relating Event and Trace Semantics of Hardware Description Languages

Industry standard hardware description languages like Verilog and VHDL are based on event simulation. Formal verification methods such as theorem proving and model checking are based on the analysis of sets of traces of transition systems or automata. There is a semantic gap between these two interpretations and consequently one cannot be sure that results obtained by simulation and formal verification are consistent. This paper is a step towards bridging this gap. A simple simulation cycle is specified for a Verilog-like language and it is shown how for simple examples of practical interest this can be related to a standard formal-verification-oriented model based on traces.