VLSI implementation of LNS arithmetic unit by LUT partitioning

The main motto of every electronic industry is to achieve low power. An efficient way to achieve this is by adapting different architectural modifications in the design. This paper proposes low power implementation of Logarithmic Number System (LNS) arithmetic unit on a FPGA. Power reduction is achieved by partitioning technique. The influence of partitioned memory on the power dissipated and delay required for performing arithmetic operations like add and sub in LNS are measured. Two design parameters namely MSB and LSB techniques are exploited to minimize the power dissipation. Only one of the sub-LUT is activated upon each operation which depends on MSB or LSB and also on the sign of operands. The synthesis is carried out using Xilinx ISE and the hardware is implemented on ZYBO Zynq-7000 development board. A considerable amount of reduction in power was obtained.