Improving microarchitecture design and hardware generation using micro-language IP cores

The need of rapid design space exploration, early prototype construction and high level of reuse of technical decisions about microarchitecture in hardware design field actualize development of technologies based on custom user-specified hardware generation. However, existing approaches and tools typically offer configurability at the level of predefined set of parameters. In the article, the concept of framework architecture based on Micro-Language IP (MLIP) cores is presented. This approach facilitates creation of lightweight hardware description languages adapted to specific microarchitectural patterns. Furthermore, prototype implementation of the framework is described, followed by description of two experimental MLIP cores, rtl and pipe. These cores provide domain-specific languages for procedural generation of general-purpose RTL and pipelined hardware structures respectively. The developed means have been utilized for rapid designing of educational CPU core that has proved its operational capability in FPGA. We envision complementation of procedural hardware generation approach with microarchitecture-specific DSLs to be promising for raising the level of abstraction in microarchitecture design. This can reduce design duration of complex hardware units by up to two times, assuming either usage of common microarchitectural patterns or embodying of original ones in the new MLIP cores as an integral part of hardware design process.