A call-up for circuit-switched NoCs in the Dark-Silicon Era

Networks-on-Chip (NoCs) are the backbone of communications in MPSoCs and future Many-Cores. The approaching thousand cores technology, together with the dark silicon era, put energy-efficiency on top of the challenges for future NoC-based multicore chips, where NoCs significantly contribute to the total chip power. This paper explores the use of circuit-switched (CS) NoCs as a low complexity energy-efficient solution for future platforms in the Dark-Silicon (Si) era. We present a thorough analysis for circuit-switched NoCs from hardware synthesis perspective at different threshold voltage (Vth) and supply levels. Based on this analysis, we further propose a Dark-si inspired multilayered-CS-NoC architecture. The proposed NoC is implemented as a mixed Vth double layered design, where each layer is optimized for a frequency level at a different supply voltage. Layer switching is explored on a per-router-port granularity level; links are either reserved on the fast or the slow layer based on the speed requirements, while the other layer is kept dark. The proposed NoC architecture is synthesized using Synopsys Design Compiler for SAED90nm technology. The obtained results show energy savings up to 34% compared to conventional single-layer single supply CS-NoCs.