Exploration of FPGA architectures for tight coupled accelerators in a 22nm FDSOI technology

Reconfigurable microprocessors extend the concept of application specific instruction set processors (ASIPs) to allow customization at runtime. Previous research mainly focused on exploiting this feature in high-level applications, without regard to the design and architecture of the reconfigurable hardware. In contrast, this paper explores the design space for tight coupled, fine-grained accelerators with a detailed physical model. We performed a comprehensive exploration of architectures for generic island-style field programmable gate arrays (FPGAs) with a custom benchmark set, a flexible toolchain, and a commercial 22nm FDSOI technology. To annotate FPGA architectures with plausible estimates for area and delay, we improved existing physical models with a customized area model. Multiple layouts validate the accuracy of this model and show that assumptions of prevailing area models do not capture layout restrictions of advanced technology nodes. Results indicate an almost constant area delay product for lookup tables (LUTs) with three to five inputs. Clusters with few logic elements or small LUTs appear to be less efficient than previously thought.