Advanced Packaging and Heterogeneous Integration to Reboot Computing

In the past several decades on-chip dimensions have scaled over 2000X, while dimensions on printed circuit board have scaled 4-5X. This modest scaling of packaging dimensions has severely limited system scaling. To address this, we have proposed a disruptive package-free integration scheme. We replace the traditional organic printed circuit board (PCB) with silicon interconnect fabric (SiIF) and replace the traditional package by directly mounting bare chiplets on to the SiIF. Fine pitch solderless copper pillar connections increase IO density by 20-80X and the inter-chiplet spacing is reduced by 10-20X. This enables highly parallel communication instead of serialized links. This achieves higher bandwidth/mm (~100X) and lower latency (~25X) and lower communication energy per bit (~200X). This integration technology allows us to challenge the conventional communication-limited architectures in a substantial way. The ability to heterogeneously integrate diverse dies with arbitrarily fine granularity, but on a wafer scale, reduces the cost of processor-memory communication energy opening new compute paradigms. In addition, the superior heat spreading properties of the SiIF compared to organic PCBs allows us to run the cores harder. The heterogeneous integration property of our scheme, allows for an intimate mingling of heterogeneous processor cores, FPGAs and memory types opening new avenues to reboot computing.