A New Concept for Computing Using Interconnect Crosstalks

Device, interconnect scaling and interconnection bottleneck are among the major challenges for CMOS scaling. Furthermore, signal integrity issues like crosstalk-leakage of charge between capacitively coupled nets among neighboring signal lines-is becoming inexorable. We propose to astutely turn this detrimental effect into an advantage by engineering the interference among signal lines. Our proposal can potentially solve scaling challenges by reducing device and interconnect scaling requirements while complying with existing manufacturing paradigm. Central to our approach is the deterministic emulation of aggressor-victim scenarios in metal lines to achieve logic computation. The metal lines that carry inputs are called aggressor nets (number of aggressor nets is proportional to fan-in of the logic gate), and output signal carrying metal lines are called victim nets; aggressor nets are coupled to victim net through virtual lateral capacitance. As a result of input transitions on the aggressor nets, summation of aggressor nets charges is introduced on the victim net. The summation signal on victim net serve as outputs for logic gate, or used to control a pass transistor to get desired logic output. Depending on the boolean logic being computed, this sum of charges seen by victim net is controlled primarily by engineering the capacitance between aggressors and victims and by synchronous clocking. We have implemented basic gates including AND, OR and XOR, and compound logic circuits following this principle. Our results indicate huge potentials for compact and low-power computing using the proposed approach.