High performance sub-0.2 /spl mu/m gate length PMOSPETs with source/drain extensions fabricated by plasma doping

High performance, sub-0.2 /spl mu/m gate length PMOSFETs with source/drain extensions formed by BF/sub 3/ plasma doping (PLAD) were successfully fabricated from a dual gate, shallow trench isolated, 0.25 /spl mu/m CMOS technology. The as-implanted junction depth of the source/drain extension fabricated by PLAD matches that of a high dose, 5 keV BF/sub 2//sup +/ implanted source/drain extension. A 1000/spl deg/C, 30 s RTA was used for activation. Both thermal and nitrided oxides of 2.8 nm physical thickness were used. In general, the PMOS devices fabricated by PLAD exhibit sub-threshold swing, off-state leakage, and hot-carrier reliability similar to the implanted ones. In addition, higher drive currents are seen in the plasma-doped devices. These improvements are attributed to reduced source/drain resistance and higher inversion gate capacitance due to better activation with PLAD. Both plasma-doped and beamline-implanted devices with nitrided oxides show similar long-channel threshold voltages, which suggests that plasma doping does not introduce additional boron penetration. The 0.18-/spl mu/m gate length, plasma-doped PMOSFETs achieve a drive current of 350 /spl mu/A//spl mu/m with an I/sub off/ of 2.5 pA//spl mu/m at 2.5 V.