Superior latch-up resistance of high dose, high energy implanted p/sup +/ buried layers

Implantation of high dose, high energy blanket boron buried layers into p-type silicon is becoming increasingly attractive for leading edge CMOS technology. Implanted p/sup +/ buried layers provide several device and circuit benefits, such as superior latch-up immunity as compared to thin epi, and secondary defect gettering of other point defects. We have demonstrated that a 1/spl times/10/sup 15/ cm/sup -2/ 1.7 MeV boron buried layer combined with a low dose connecting layer produces latch-up trigger currents in excess of 1000 /spl mu/A//spl mu/m, while the n/sup +//p/sup +/ spacing was only 0.4 /spl mu/m. This is much higher than what has been reported on epi substrates. The leakage currents for the 250 nm devices were significantly lower than the unimplanted controls or wafers with lower buried layer doses, indicating sucessful damage gettering. Other device parameters such as threshold voltage, saturation current and punch through voltage were unaffected by the buried layer. The unique properties of the implanted p+ buried layer provide the CMOS process designer with many technical advantages, as will be discussed.