Effect of energy reduction in sub-keV boron implantation on ultra-shallow junction formation

Ultra-shallow junctions under 50 nm are required at source/drain (S/D) region for deep sub-quarter micron devices. Reduction in implantation energy has been an effective way for realizing shallower junctions, due to the elimination of transient enhanced diffusion (TED). However, the effect of energy reduction in sub-keV boron implantation has not been clarified. An additional diffusion-enhanced mechanism has been previously reported in this energy region. In addition, low beam current will be the problem to apply sub-keV implantation to device manufacturing. Decel mode implantation has been developed for increases in beam current; however, the influence on device performance has not been evaluated. In this work, we investigate the effect of implantation energy reduction on sub-micron PMOS-FETs and the device effect of energy contamination when using decel mode implantation. In this work, B was implanted into S/D extension regions at 0.2-0.5 keV, 5/spl times/10/sup 14//cm/sup 2/ by drift mode. After deep-S/D implantation, samples were annealed at 950/spl deg/C for 10 sec. The junction depth was decreased from 31.2 nm down to 23 nm by reducing the B energy from 0.5 keV to 0.2 keV. This shows that the reduction of B energy is effective to realize shallower junction in sub-keV region. Threshold voltages (Vt) were measured for PMOS-FETs with gate length from 0.15 /spl mu/m to 1 /spl mu/m. The Lmin, which indicates the short channel effect, was improved 5% by the reduction of B energy from 0.5 keV to 0.2 keV. This shows that the energy reduction is also effective to decrease the B lateral diffusion at the short channel region. To investigate device effects of energy contamination at 0.5 keV implantation, B was implanted before the S/D extension implantation at 2-5 keV, 5/spl times/10/sup 12/-2.5/spl times/10/sup 13//cm/sup 2/ as a 1-5% contamination element. We found that acceptable energy contamination is under 3% for 2 keV for 0.15 /spl mu/m devices. And, 10% fluctuation of energy contamination at 2 keV 3% energy contamination is acceptable.