A 5.8 GHz Digitally Controlled CMOS Receiver With a Wide Dynamic Range for Chinese ETC System

This brief presents a 5.8 GHz digitally controlled dedicated short range communications (DSRC) receiver for Chinese electronic toll collection systems. All RF, IF blocks and digital baseband for on-chip automatic gain control, are integrated on an RF system-on-chip (RF-SoC). The proposed digitally controlled low noise amplifier (LNA) and mixer circuits are elaborated. The test chip was realized in a 0.13-μm CMOS technology. The RF blocks in receiver occupy a chip area of 0.75 mm
²
. The receiver blocks consume 22 mA under a 1.5-V supply voltage. Measurement results show that the bit error rate maintains better than 10
^-6
, while the input power level varies from -75 dBm to -8 dBm. This design results in a receiver sensitivity improvement of at least 25%, and a dynamic range enhancement of at least 12%.