Read Error Resilient MLC STT-MRAM Based Last Level Cache

STT-MRAM is a promising non-volatile memory technology for building large LLCs (Last Level Caches). Multi-level cell (MLC) STT-MRAM can further enlarge cache capacity with reduced per bit cost. However, due to fast technology scaling, STT-MRAM, in particular, MLC STT-MRAM, suffers from significant read errors, including read disturbance errors and sensing errors, which lead to unreliable accesses that prevent the adoption of MLC STT-MRAM in LLCs. In this paper, we propose R2M, a read error resilient 2T4J (two transistor four MTJ) MLC based LLC design. R2M leverages the recently industry-proposed 2T2J single-level cell (SLC) structure to achieve good tradeoff between reliability and capacity. It consists of two schemes: R2M-S and R2M-C. R2M-S improves read reliability by sensing the resistance difference of two cells, which effectively mitigates both sensing and disturbance errors for the soft bit of MLC. R2M-C further enhances error resiliency by exploiting access locality and data redundancy. We evaluate the proposed R2M design and compare it to the state-of-the-art. Our experimental results show that, on average, R2M achieves 54.8% performance improvement and 42.0% energy consumption reduction over the state-of-the-art MLC design.