Automatic Protocol Compliance Checking of SystemC TLM-2.0 Simulation Behavior Using Timed Automata

The increasing complexity of todays digital circuit designs led to the increased usage of abstract models. In particular, the Electronic System Level (ESL) has emerged as an area of active research. For ESL design, SystemC and its Transaction Level Modeling (TLM) framework have become the standard tools for abstract modeling. The resulting models represent both, an executable specification and a reference model for the hardware design. The correctness of these designs is important as undetected errors may propagate to less abstract levels in the design process, increasing the potential amount of work required to fix them. To quickly ensure that implementations and reference emit the same behavior, the comparison between these abstractions needs to be both, flexible and automated. This paper presents a method to verify the simulation behavior of a given System TLM-2.0 design against TLM-2.0 protocols. The system's structural description and its run-time behavior are translated to a single, consistent formal model. This is then used to verify that a simulation run adheres to a given protocol. The protocol compliance checks are performed using the UPPAAL model checker and applied to several TLM models.