Low power and area efficient FFT architecture through decomposition technique

Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) is an integral part of Orthogonal Frequency division multiplexing (OFDM) systems. This forms the physical layer architecture of wireless systems and is designed to consume low power. This paper presents a low power and area efficient architecture for the FFT implementation. FFT involves more complex addition and multiplication operations. It is essential to reduce computational complexity of this FFT. Hence, the redundancies in intermediate stages of FFT is minimized in the proposed FFT architecture through decomposition techniques with reusable data approach. A common sub expression is identified to achieve reusability which leads to area and power efficient design. Also design is realized based on Multiplierless arithmetic unit with retiming logic. FFT architecture is synthesized using Xilinx ISE Tool, and compared with the results so obtained with the Xilinx IP core 7.1. The power reduction, and area optimization is shown to be improved by 6% and 74% respectively.