Robust high speed ASIC design of a vedic square calculator using ancient Vedic mathematics

This paper proposed a design of a new square calculator using the ancient Vedic mathematics for Application Specific Integrated Circuit (ASIC). This is a robust and novel approach to design the Vedic calculator. The squaring of a number is the procedure of self multiplication. The ancient Vedic mathematics has a set of 16 sutras & 13 sub sutras. In this paper, the sutra `Urthava Triyakbhym' and `Nikhilam Navatascaramam Dasatah' is used to find out the square of an integer number quickly. The circuit design in this regard has been proposed here and is possibly the simplest one yet so far. Simulation of the circuit has been carried out using Xilinx ISE software.