Enhanced bipolar transistor design for the linearization of the base-collector capacitance

A frequency, bias and output power independent linearization technique for reducing the non-linear base-collector capacitance related distortion is proposed. Based on Volterra series analysis, the optimum base-collector capacitance for linear device operation is determined while respecting physical constrains. It is shown that by modifying the extrinsic base-collector region for an otherwise uncompromised device, the C
_bc
linearity compensation can be included within the transistor design itself. The practicality of this implementation is demonstrated by considering the doping profile accuracy requirements for achieving a significant OIP3 improvement of at least 5dB.