The current state of evolution of content addressable memory architecture and aspects of its usage in the PDCS “Buran”

The article provides an overview of the main directions of the development of architectures of content addressable memory and associative processors. The main problems that are facing the developers of these devices are identified. The description of the content addressable memory of keys in the matching processor, which is the main computation process control device in the parallel dataflow computing system (PDCS) “Buran”, is given. Existing methods to increase the speed and reduce power consumption for various types of content addressable memory (CAM, TCAM, etc.) are considered. Various TCAM architectures implemented on the nonvolatile memory technology, as well as associative processors are described.