A 250-MHz Pipelined ADC-Based $f_{S}/4$ Noise-Shaping Bandpass ADC

A new f
_S
/4 bandpass ΔΣ-analog-to-digital converter (ADC) architecture is realized by feeding back the delayed quantization noise inherently produced by a pipelined ADC. Designed in a 55-nm global foundry (GF) LP-CMOS process, the prototype ADC sampling at 250 MHz achieves an Signal-to-Noise+Distortion Ratio of 72, 75.8, 80.1, and 85.3 dB in a 15.64-, 7.82-, 3.91-, and 1.953-MHz band, respectively, around a center frequency of 62.5 MHz with only first-order noise shaping, while consuming 103 mW of power, and achieving a maximum figure-of-merit of 158 dB.