On Enhancing Reliability of Weak PUFs via Intelligent Post-Silicon Accelerated Aging

SRAM-based weak physically unclonable functions (PUFs) have shown promise regarding tamper sensitive key storage and device ID generation. Weak PUFs rely on intrinsic process variations to produce repeatable and unique start-up behavior. However, noise in the system can affect the start-up behavior and introduce errors. A number of solutions, such as fuzzy extraction and error correcting codes have been proposed to alleviate the effect of noise and generate stable keys. Unfortunately, the overhead from these techniques grows superlinearly with increasing error rate. Alternatively, accelerating device aging or burn-in has been shown to reduce start-up error rate significantly, which leads to reduced overhead for error correction. Unfortunately, burn-in is a time-intensive process and accrues significant production cost. This paper proposes a method to reduce the cumulative burn-in time via quantification of the minimum burn-in requirements for chip. We propose a low-cost proxy to measure the degree of process variation of each device at birth and use previously proposed device aging models to determine the burn-in requirements. Our results show that this procedure reduces cumulative burn-in cost without compromising the resultant reliability of weak PUFs. Furthermore, we analyze the effect of having additional PUF cells, alternate weak PUF designs and transistor technologies on burn-in requirements.