Computationally Minimized X-Part for FX Correlator in Big-Data Interferometers

Big-data is a challenging domain for high-throughput digital signal processing (DSP), especially in global-projects like the square kilometer array. The composite input data rate for correlator in this system is more than 11 Tb/s, which immensely increases the memory requirement, complexity of correlation implementation and the overall power dissipation. This paper is focused on computational minimization as well as the improvement of energy efficiency in the complex architectural X-part of an FX correlator employed in large array radio telescopes. A dedicated correlator-multiplier block termed, correlator-system-multiplier-and-accumulator (CoSMAC) cell architecture is proposed, which produces two 16-b integer complex multiplications within the same clock period. The novel hardware optimization is achieved by utilizing the flipped mirror relationship (conjugate complex symmetry) between discrete Fourier transform (DFT) samples owing to the symmetry and periodicity of the DFT coefficient vectors (twiddle factors). In addition, using the proposed CoSMAC architecture a new processing element (PE) is designed to calculate both the cross- and auto-correlation functions within the same clock period. This paper describes how the arithmetic processing of three baseline calculations will be minimized in the X-part using the proposed novel algorithm and hardware design (CoSMAC and PE). In addition to optimizing the core processing elements, it is possible to eliminate nearly 50% of the usual memory requirement. The design has been synthesized using global foundries 28-nm HPP CMOS standard cells.