Investigation of Retention Characteristics for Trap-Assisted Tunneling Mechanism in Sub 20-nm NAND Flash Memory

In this paper, retention characteristics of the trap-assisted tunneling (TAT) mechanism are investigated in sub 20-nm NAND flash memory. Total charge loss source for the TAT mechanism (
$ {\Delta V_{\rm th({\mathrm{ TAT}})}}$
) becomes larger with baking temperature, while the source for the detrapping mechanism is almost constant. This temperature dependence of the TAT mechanism becomes larger as program/erase cycling stress increases. Also, this trend is much larger in the highest programmed threshold voltage distribution state. By comparing activation energies of the TAT and the detrapping mechanisms, it was found that the TAT mechanism is very affected by trap density as well as the strength of the electric field in the tunneling oxide layer. To scale down, lifetime of the device can be rapidly reduced due to the decreased time-constant (
${\tau }$
) of the TAT mechanism.