A run-pause-resume silicon debug technique for multiple clock domain systems

The run-pause-resume (RPR) debug methodology allows one to pause the normal circuit operations, observe the internal states of flip-flops and then resume the normal operations for further debug process. Data invalidation is a major problem that needs to be addressed when debugging a multiple-clock design with this methodology. This problem occurs when flip-flops in a receiving clock domain capture incorrect data during debugging, and thus cannot be resumed correctly. In this paper we propose a novel RPR technique that can avoid data invalidation with the cycle-level granularity of debug resolution. A software program is employed to calculate the exact time to transmit pause control signals according to the user-defined breakpoint and a hardware controller is developed to convert the pause signal to appropriate gating signals for the circuit under debug (CUD) and the data path of the clock domain crossing interface. By doing this, we can avoid data invalidation as well as allow users to pause and resume the CUD at arbitrary clock cycle. Experimental results show that the hardware area overhead is very small and 100% debug resolution is achieved.