A phase-locked loop based on cascaded least-error squares filter

Phase-locked loops (PLLs) are very important in power and energy areas. Many PLLs have been proposed in recent literatures, and all these methods are to design a robust filter and let them be as a preprocessing tool before the synchronous reference frame PLL (SRF-PLL) input. Among these PLLs, a interesting PLL is Least-Error Squares (LES) Filter-Based PLL (LES-PLL), which is composed of a LES filter and a SRF-PLL. This paper does several works about LES filter-based PLL. First, through analyzing LES filter, a conclusion is that the LES filter can eliminate arbitrary harmonic series by appropriately configured, which is not proposed before. Secondly, a cascaded LES (CLES) filter is proposed to deal with the issue that the high complexity of LES filter when it is used to eliminate too much harmonics. Finally, based on CLES filter, CLES-PLL is proposed. And a realization of frequency adaptability of CLES-PLL is presented, which has low computational advantage compared with other method. To verify the effectiveness and robust performance of proposed CLES-PLL, experiments are carried out.