A comprehensive study on the gate-loop stability of the SiC MOSFET

Silicon carbide (SiC) MOSFETs have been widely studied in high frequency applications. The switching performance, however, is limited with the existence of the parasitic elements. One critical issue is the susceptibility of the gate-source voltage to the parasitic elements, rendering the possibility of spurious operation of the SiC MOSFETs. This paper conducts comprehensive investigations on the impact of parasitic elements on the gate-source voltage of the SiC MOSFET at switch turn-on and turn-off. It is found inappropriate circuit design can cause aggravation of the oscillations of the gate-source voltage of the SiC MOSFET, further leading to the occurrence of unintended switching events. Equivalent circuit models are utilized to study the oscillations in the gate-loop. The effects of parasitic elements on the gate-loop stability are studied through PSpice simulation and experiments. Based on the results, piratical suggestions on the circuit design and control are made to designers.