Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET

A 12 b 600 MS/s 2 × TI SAR ADC achieving 60 dB SNDR at Nyquist is presented. Time-interleaving errors are calibrated in the background by using a linear but noisy reference ADC. A test chip demonstrates that interleaving spurs are reduced to below −70 dBFS using an off-chip least-mean-squares (LMS) algorithm. The reference ADC is an 8 b SAR with reduced sampling capacitance and input amplitude. This results in a low-power reference ADC with high bandwidth and low harmonic distortion. Linearity errors introduced by capacitor mismatch are reduced with dynamic element matching (DEM). The LMS algorithm also calibrates third-order harmonic distortion. The noise of the reference ADC is averaged in the LMS algorithm. Hence, it allows us to combine the high linearity of the reference ADC with the low-noise performance of the main ADC. The total power consumption, including clock generation and input buffers, is 38.5 mW. The reference ADC running at 200 MS/s contributes 2.2 mW to the total power.