Fault emulation on heterogeneous architectures

This paper presents implementation of fault emulation method which is very important in today's chip tests on a platform with heterogeneous architecture. Nowadays, the increase in the number of transistors in electronic circuits put fault emulation method forward which is faster than fault simulation in order to obtain a test set against possible defects on chips. In this method, a hardware model of the chip to be designed is implemented on Field Programmable Gate Arrays (FPGA) and it becomes possible to obtain a test set by applying different fault models. Heterogeneous architectures, on the other hand, provide energy savings and speed advantages over traditional architectural approaches as they involve different units in the execution of different workloads besides the central processing unit (CPU). Furthermore, multi-cycle tests are important because they can catch more errors with the same test vector than single-cycle tests. In this paper, as an application, it is explained the fault emulation of multi-cycle tests in a heterogeneous platform which employs FPGA and the results are shown.