A combination of a digital foreground and background calibration for a 16 bit and 200MS/s pipeline analog-to-digital converter

High-Performance Analog-to-Digital Converter (ADC) have high requirements concerning sampling rate and linearity. Therefore a new formula is derived to determine, which pipeline stage dependent on the used capacitor sizes needs to be calibrated for the targeted linearity. Furthermore, a model of a 16 bit and 200 MS/s pipeline ADC is described. A combination of a digital foreground and a digital background calibration is presented, which can compensate linear errors and achieves a DNL smaller than ±1 and a THD of −88 dB.