Delay estimation and measurement circuit for a high-speed CMOS clocked comparator

Comparators are a critical element of Analog-to-Digital converters (ADCs) intended to operate in a harsh environments such as the automotive. The influence of temperature on key comparator properties such as the delay must be well understood to maximize their speed. In this paper a Double-Tail latch analysis leads to an analytical expression for the delay to more accurately guide the design over a wide temperature range. The results given by this model agree well with spice postlayout simulation for a CMOS 0.18-μm SOI process, taking into consideration both process and temperature variations. To verify experimentally the correctness of the model we also propose a novel on-chip fully digital asynchronous architecture to measure the delay of the comparator, robust against extreme temperature variations.