Hardware design of a wearable ECG-sensor: Strategies implementation for improving CMRR and reducing noise

In this paper is presented the electronic design of a wearable electrocardiograph (ECG) circuit considering a two-electrodes ground free optimized model, a collection of hardware filters to reduce RF interference and a Driven-Right-Leg Circuit Design to improve the Common-Mode Rejection. Nowadays, large attention is given to the development of innovative wearable system able to monitor physio-pathological parameters of individuals. Heart disease remains the leading killer of adults over age 65. This paper presents some innovative hardware solutions to implement a low cost, high performance and user friendly device.