Single-event upset responses of dual- and triple-well designs at advanced planar and FinFET technologies

Single-event upset (SEU) responses of advanced dual- and triple-well planar technologies show significant differences in SEU cross-section for memory cells. The presence of the third well alters the charge-collection mechanism as well as increases the probability of charge sharing, affecting the SEU responses of memory cells. However, at the 16-nm FinFET technology node, heavy-ion experiments show insignificant differences in SEU cross-section between dual- and triple-well flip-flop (FF) designs operated at nominal supply voltage. When the supply voltage is reduced, SEU responses of dual-well and triple-well designs show differences for particles with low LET values, but not for particles with high LET values. 3D TCAD simulations show insignificant differences in contributing single-event transient (SET) pulse width for dual- and triple-well technologies at nominal supply voltage. For low LET particles at reduced supply voltage, the resultant SET pulse width for the triple-well design is smaller compared to that for the dual-well design, leading to a decrease in triple-well SEU cross-section.