ANYSYS chip-level and wafer-level simulation on semiconductor process development — Yu-Chih Chang

Most of simulation activities implemented on semiconductor manufacturing are focus on the device characteristics, and electrical properties. Less investigation pays attention on micro-structure stress/strain calculation with finite element analysis. This investigation demonstrates the ANSYS simulation results match with real cases results. The chip-level micro-structure simulations include the metal grain size behavior influence the BEOL leakage electrical properties; different design layout causes stress concentration issue, and different collapsed behavior induced by surface tension after wet strip. The wafer-level macro-structure simulation demonstrates that different pattern density of design will affect bow height performance in whole wafer. By means of ANSYS analysis, we can achieve more experiments or DOE splits by perdition simulation instead of real wafers and experiments. Thus, we can save the cost and achieve the time-to market requirement during product development.