Dual port SRAM read-disturb-write mechanism and design for test

Dual Port (DP) needs asynchronous clock skew test to screen out read-disturb-write during simultaneous row access from both ports. We will explain read-disturb-write failure mechanism from simulation and Si. The BL clamped design and longer write word-line-pulse scheme can improve DP Vmin. 2D adaptive shmoo is also proposed to reduce test time.