A 34fJ/conversion-step 10-bit 6.66MS/s SAR ADC with built-in digital calibration in 130nm CMOS

A 10-bit single-channel SAR ADC is designed in a 130nm CMOS technology. An original DAC is proposed, merging a binary-weighted structure and a C/2C topology in order to reduce overall energy consumption. A built-in calibration circuit improves the conversion accuracy. The proposed SAR ADC samples at 6.66MHz, achieving a SNDR of 49.78 dB for a 1MHz input signal (ENOB of 8 bits). The simulated INL is in the order of ±2 LSB, while consuming only 58uW under a supply voltage of 1V. The resulting FOM is 34fJ/conversion-step.