Low-power multi-size HEVC DCT architecture proposal for QFHD video processing

The demand for higher quality video has increased in the past few years, due to the huge amount of electronic devices that process digital video in even higher resolutions. For that purpose, video coding techniques are used, which have, as main goal, the reduction of the required representation to process a digital video. Furthermore, embedded hardware video solutions are sought for both industry and academia. Therefore, low-power consumption is required for those battery-based devices. This work proposes 1-D architecture for the DCT (Discrete Cosine Transform) module of the HEVC video coding standard. Furthermore, the proposed work implements a digital hardware structure able to process all the four sizes of residual matrixes, by using a purely combinational fashion. Statistical analyses were made, using real video sequences as input. Based on these analyses, energetic efficiency is achieved by inserting a low-power technique, without significant prejudice to the architecture performance. Synthesis results showed that the architecture has the lowest proportional power consumption along related works by using an accurate power estimation with the use of real video sequences as stimuli for the gate-level simulation, while it is still able to process QFHD videos at 32 frames per second.